1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
In recent years, thinning and downsizing of a semiconductor device and its package have been further required. Because of that, a flip-chip type semiconductor device, in which a semiconductor element such as a semiconductor chip is mounted on a substrate by flip-chip bonding (flip-chip connected), has been widely used as a semiconductor device and its package. In the flip-chip connection, the circuit surface of a semiconductor chip is fixed to the electrode forming surface of the substrate in a way that the circuit surface is facing to the electrode forming surface. After the flip-chip connection, the space between the semiconductor element and the substrate is filled with a sealing resin in order to protect the surface of the semiconductor element and to secure connection reliance between the semiconductor element and the substrate. A liquid sealing resin has been widely used as such a sealing resin. However, it is difficult to adjust the filling position and the filling amount of the liquid sealing resin. Then, a technique has been proposed in which a sheet-like sealing resin is used to fill the space between the semiconductor element and the substrate (Japanese Patent Application Laid-Open No. 10-289969).
Further, a three-dimensional mounting technique, in which semiconductor elements are laminated in a plurality of layers in the thickness direction, has been developed for the purpose of high density integration of a semiconductor element. Examples of a semiconductor element that is used in the three-dimensional mounting technique include semiconductor elements that are referred to as TSV (Through Silicon Via) type semiconductor elements in which members for connection, such as bumps that are formed on both surfaces of the semiconductor element, are electrically connected through a via. The member for connection is formed in advance so that the position of the member for connection of the semiconductor element in the lower layer (substrate side) corresponds to the position of the member for connection of the semiconductor element in the upper layer, to perform the three-dimensional mounting more easily and securely.